SE CSE SEM 3 – DIGITAL LOGIC & COMPUTER ARCHITECTURE

Module 1- Computer Fundamentals
9 Topics
1.1 Introduction to Number System and Codes
1.2 Number Systems: Binary, Octal, Decimal, Hexadecimal
1.3.a Codes: Grey, BCD, Excess-3
1.3.b ASCII code
1.3.c Boolean Algebra
1.4 Logic Gates: AND, OR, NOT, NAND, NOR, EX-OR
1.5 Overview of computer organization and architecture
1.6.a Basic Organization of Computer and Block Level functional Units
1.6.b Von Neumann Model
Module 2- Data Representation & Arithmetic Algorithms
7 Topics
2.1.a Binary Arithmetic: Addition, Subtraction, Multiplication, Division using Sign Magnitude
2.1.b Binary Arithmetic: 1’s and 2’s compliment
2.1.c BCD Arithmetic Operation
2.1.d Hex Arithmetic Operation
2.2.a Booths Multiplication Algorithm
2.2.b Restoring and Non-restoring Division Algorithm
2.3 IEEE-754 Floating point Representation
Module 3 – Processor Organization & Architecture
11 Topics
3.1.a Introduction: Half adder
3.1.b Full adder
3.1.c MUX
3.1.d DMUX
3.1.e Encoder, Decoder
3.2 Introduction to Flip Flop: SR, JK, D, T
3.3.a Register Organization
3.3.b Instruction Formats
3.3.c Addressing modes
3.3.d Instruction Cycle
3.3.e Interpretation and sequencing
Module 4 – Control Unit Design
6 Topics
4.1.a Hardwired Control Unit: State Table Method
4.1.b Delay Element Methods
4.2.a Microprogrammed Control Unit: Micro Instruction-Format
4.2.b Sequencing and execution
4.2.c Micro operations
4.2.d Examples of microprograms.
Module 5 – Memory Organization Fractal Generation
11 Topics
5.1.a Introduction and characteristics of memory
5.1.b Types of RAM and ROM
5.1.c Memory Hierarchy
5.1.d 2-level Memory Characteristic
5.2.a Cache Memory: Concept
5.2.b Locality of reference
5.2.c Design problems based on mapping techniques
5.2.d Cache coherence
5.2.e Write policies
5.2.f Memory Interleaved
5.2.g Associative Memory
Module 6 – Interleaved and Associative Memory. 6 -Principles of Advanced Processor and Buses
13 Topics
6.1.a Basic Pipelined Data path and control
6.1.b Data dependencies
6.1.c Data hazards
6.1.d Branch hazards
6.1.e Delayed branch
6.1.f Branch prediction
6.1.g Performance measures
6.1.h CPI, Speedup, Efficiency, throughput, Amdhal’s law
6.2 Flynn’s Classification, Introduction to multicore architecture.
6.3.a.1 Introduction to buses – ISA
6.3.a.2 Introduction to buses – PCI
6.3.a.3 Introduction to buses – USB
6.3.b Bus Contention and Arbitration.
Previous Lesson
Next Lesson

Module 2- Data Representation & Arithmetic Algorithms

SE CSE SEM 3 – DIGITAL LOGIC & COMPUTER ARCHITECTURE Module 2- Data Representation & Arithmetic Algorithms
Lesson Content
0% Complete 0/7 Steps
Previous Lesson
Back to Course
Next Lesson