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Mar’24 month certification
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SE EXTC SEM 3 – DIGITAL SYSTEM DESIGN

Course Content

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Module 1 – Number Systems and Codes 8 Topics

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Lesson Content

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1.1.a – Review of Binary

1.1.b – Octal and Hexadecimal Number Systems

1.1.c – Their inter-conversion

1.1.d – Binary code

1.1.e – Grey code and BCD code

1.1.f – Binary Arithmetic

1.1.g – Addition

1.1.h – Subtraction using 1’s and 2’s Complement

Module 2 – Logic Family and Logic Gates 8 Topics

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2.1.a – Difference between Analog and Digital signals

2.1.b – Logic levels

2.1.c – TTL and CMOS Logic families and their characteristics

2.2.a – Digital logic gates

2.2.b – Universal gates

2.2.c – Realization using NAND and NOR gates

2.2.d – Boolean Algebra

2.2.e – De Morgan’s Theorem

Module 3 – Combinational Logic Circuits 14 Topics

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3.1.a – SOP and POS representation

3.1.b – K-Map up to four variables and Quine-McClusky method for minimization of logic expressions

3.2.a – Half adder

3.2.b – Full adder

3.2.c – Half Subtractor

3.2.d – Full Subtractor

3.2.e – Carry Look ahead adder and BCD adder

3.2.f – Magnitude Comparator

3.3 – Multiplexer and De-Multiplexer:

3.3.a – Multiplexer operations

3.3.b – cascading of Multiplexer

3.3.c – Boolean function implementation using MUX

3.3.d – DEMUX and basic gates

3.3.e – Encoder and Decoder

Module 4 – Sequential Logic Circuits 21 Topics

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4.1.a – Flip flops:

4.1.a3 – Master slave flip flops

4.1.b – T & D flip flops with various triggering methods

4.1.c – Conversion of flip flops

4.1.d1 – SISO

4.1.d2 – SIPO

4.1.d3 – PISO

4.1.d4 – PIPO

4.1.d5 – Universal Shift Register

4.2 – Counters:

4.2.a – Asynchronous and Synchronous counters with State transition diagram

4.2.b – Up/Down

4.2.c – MOD N

4.2.d – BCD Counter

4.3 – Applications of Sequential Circuits:

4.3.a – Frequency division

4.3.b – Ring counter

4.3.c – Johnson counter

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Module 5 – Memories and Programmable Logic Devices 9 Topics

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5.1.a – Classification and Characteristics of memory

5.1.f – EPROM and Flash memories

5.2.a – Programmable Logic Devices(PLD)

5.2.b – Programmable Logic Array(PLA)

5.2.c – Programmable Array Logic(PAL)

Module 6 – Introduction to VHDL 4 Topics

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Lesson Content

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6.1.a – Basics of VHDL/Verilog Programming

6.1.b – Design and implementation of adder

6.1.c – Subtractor

6.1.d – Multiplexer and flip flop using VHDL/Verilog

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